Arrogant Professors Suck!
So for the last two weeks, I have been one of the first students in my class to work on and finish a homework and lab assignment due in a class of mine. I had the lab completed up to a point were I kept getting errors in the computer program. I thought maybe it was a problem with the code I was writing, so I rewrote the thing countless times. Then yesterday, I found out that no one has been able to do what I've had problems with. Not even the "Program Guru" Anshul knew what was wrong. Anshul is supposed to know everything. So I volunteer to email the professor and tell him what is up:
Dr. Arrogant,
I have talked to both Bonita and Anshil and we are all hitting an error. We have made a VHDL file of the full adder, and then ran it in leonardo. This makes a new VHDL file with less gates in it. However, when we try to compile the new file so we can synthesize it using vsim, we come across the following errors:
** Error: fulladder_1.vhd(94): Unknown identifier: ao2a0
** Error: fulladder_1.vhd(94): Unknown component name
** Error: fulladder_1.vhd(95): Statement cannot be labeled.
** Error: fulladder_1.vhd(95): Unknown identifier: xr2t0
** Error: fulladder_1.vhd(95): Unknown component name
** Error: fulladder_1.vhd(96): Statement cannot be labeled.
** Error: fulladder_1.vhd(96): Unknown identifier: xr3t0
** Error: fulladder_1.vhd(96): Unknown component name
** Error: fulladder_1.vhd(97): VHDL Compiler exiting
I talked to Dr. B, and he hypothesized that a library file might have been moved in the updating. Anshul, Bonita, and a few members in class could not figure this out. Could we try and address this in Friday's class? That way everyone will be able to turn in the homework on Monday.
Thank you for your help!
[Robohood]
I thought I was being responsible since I am apparently the only one to tell him there was a problem. However, this is the response I get:
I have checked and it's the tools issue. I will continuously check with Anshul. As you know, the homework was assigned two weeks ago; you should not have waited till the last minute. We know that those commercial CAD tools are not robust, and therefore we expect some drawbacks.
Thanks
Professor Arrogant
Dept. of Electrical & Computer Engineering
Hold on! Just wait a second! I'm working my ass off, and this guy says I'm slacking?? Fuck that! So I send off another email to as polite as possible tell him to screw off:
Dr. Arrogant,
To be perfectly honest, I had both the lab and the homework completed from the day I met you in your office a week ago. The leonardo synthesis was the only part I had not finished, and I thought the problem lie in my code. I kept rewriting the VHDL model to see if leonardo would somehow work. This isn't a last minute problem, rather the final point where I gave up trying. I didn't realize until yesterday that others were having the same difficulties. Thank you for all your help in the matter, I had no clue what I was doing wrong, and it is a relief to know it was the tools the entire time.
Thank you again for your help!
[Robohood]
Hmmm. Maybe a bit too polite. But then again, I still have a whole semester to go with this guy. Best to not piss him off too early... :-)
Dr. Arrogant,
I have talked to both Bonita and Anshil and we are all hitting an error. We have made a VHDL file of the full adder, and then ran it in leonardo. This makes a new VHDL file with less gates in it. However, when we try to compile the new file so we can synthesize it using vsim, we come across the following errors:
** Error: fulladder_1.vhd(94): Unknown identifier: ao2a0
** Error: fulladder_1.vhd(94): Unknown component name
** Error: fulladder_1.vhd(95): Statement cannot be labeled.
** Error: fulladder_1.vhd(95): Unknown identifier: xr2t0
** Error: fulladder_1.vhd(95): Unknown component name
** Error: fulladder_1.vhd(96): Statement cannot be labeled.
** Error: fulladder_1.vhd(96): Unknown identifier: xr3t0
** Error: fulladder_1.vhd(96): Unknown component name
** Error: fulladder_1.vhd(97): VHDL Compiler exiting
I talked to Dr. B, and he hypothesized that a library file might have been moved in the updating. Anshul, Bonita, and a few members in class could not figure this out. Could we try and address this in Friday's class? That way everyone will be able to turn in the homework on Monday.
Thank you for your help!
[Robohood]
I thought I was being responsible since I am apparently the only one to tell him there was a problem. However, this is the response I get:
I have checked and it's the tools issue. I will continuously check with Anshul. As you know, the homework was assigned two weeks ago; you should not have waited till the last minute. We know that those commercial CAD tools are not robust, and therefore we expect some drawbacks.
Thanks
Professor Arrogant
Dept. of Electrical & Computer Engineering
Hold on! Just wait a second! I'm working my ass off, and this guy says I'm slacking?? Fuck that! So I send off another email to as polite as possible tell him to screw off:
Dr. Arrogant,
To be perfectly honest, I had both the lab and the homework completed from the day I met you in your office a week ago. The leonardo synthesis was the only part I had not finished, and I thought the problem lie in my code. I kept rewriting the VHDL model to see if leonardo would somehow work. This isn't a last minute problem, rather the final point where I gave up trying. I didn't realize until yesterday that others were having the same difficulties. Thank you for all your help in the matter, I had no clue what I was doing wrong, and it is a relief to know it was the tools the entire time.
Thank you again for your help!
[Robohood]
Hmmm. Maybe a bit too polite. But then again, I still have a whole semester to go with this guy. Best to not piss him off too early... :-)
Comments
Sorry you had to run into a professor who tried to tear you down to make himself feel effective. Its an unfortunate hazard of the student/professor "relationship."
I try to leave a class as soon as I can --- try to size them up as arrogant and run while I can still drop the course and add another , etc. I look at the syllabus for how they word things and how tight-assed they are about rules and regulations. Best professors are the ones who show concern and balance in a situation-- which again can often be found by reading their choice of language on the syllabus and from university professor under-ground ratings, etc.
So next time-- IF YOU CAN, try to be more careful about who you enroll with. I personally think you deserved an A in the class and the rest of the semester off!
LOL
GOOD LUCK HON!